1. Field of the Invention
The present invention relates to a method for forming a minute resist pattern, and more particularly to a method for forming a resist pattern with a fine space width and for forming a gate electrode using the pattern.
2. Description of the Related Art
There have been continuous demands for an increase in the integration of semiconductor devices and an increase in the operation frequency or speed of semiconductor devices.
In order to meet the demands, it is necessary to make all the elements of a semiconductor device smaller in size. One of the elements required to be made smallest among various kinds of the semiconductor devices is a gate electrode in a compound semiconductor field effect transistor. Accordingly, there have been proposed various techniques to form a gate electrode having a small gate length.
(First Prior Art Method)
A common method for forming a conventional field effect transistor having a T-section gate electrode (or mushroom-shaped gate electrode) is shown in FIGS. 1A to 1D. In the first prior art, after forming a source electrode 2 and a drain electrode 3 on a compound semiconductor substrate 1 (FIG. 1A), a lower resist 4 is applied and formed on the source and drain electrodes 2, 3 on the semiconductor substrate 1, and an opening 5 to be the gate pattern is formed in the lower resist 4 by light exposure and development (FIG. 1B). After applying a heat treatment to the lower resist 4 at a high temperature, an upper resist 6 is applied onto the lower resist 4, and an inverted tapered opening 7 is formed in the upper resist 6, facing to the opening 5 of the lower resist 4 (FIG. 1C). Then, by depositing a gate metal on the semiconductor substrate 1 through the opening 7 of the upper resist 6 and the opening 5 of the lower resist 4, and removing the unnecessary gate electrode and resists 4 and 6, a T-section gate electrode 8 is formed by the lift-off method (FIG. 1D).
(Second Prior Art Method)
FIG. 2 shows a method for forming a minute pattern, utilizing the mixing effect of resists for realizing a minute opening size. A method related to this method is disclosed in Japanese Unexamined Patent Publication No. 5-166717. In the second prior art method, after applying a lower resist 4 onto a compound semiconductor substrate 1 with a source electrode 2 and a drain electrode 3 formed thereon (FIG. 2A), an opening 5 to be the gate pattern is formed in the lower resist 4 by exposing and developing a desired portion with an electron beam (FIG. 2B). Then, by applying a resin 9 for forming a mixing layer on the lower resist 4 so as to cover the opening 5 of the lower resist 4 (FIG. 2C), and removing unnecessary resin 9, a mixing layer 10 is formed on the lower resist 4 as well as an opening 11 is formed in the mixing layer 10 (FIG. 2D). At the time, since the mixing layer 10 covers the surface of the lower resist 4, the opening 11 of the mixing layer 10 is narrower than the opening 5 of the lower resist 4. An upper resist 6 is applied onto the mixing Layer 10, and an inverted tapered opening 7 is formed in the upper resist 6, facing to the opening 11 of the mixing layer 10 (FIG. 2E). Then, by depositing a gate metal on the semiconductor substrate 1 through the opening 7 of the upper resist 6 and the opening 11 of the mixing layer 10, and removing the unnecessary gate electrode, resists 4 and 6, and the like, a T-section gate electrode 8 is formed by the lift-off method (FIG. 2F). According to this method, since the gate length of the gate electrode 8 can be shorter by double as much as the film thickness of the mixing layer 10 compared with the case not having a mixing layer 10, a minute pattern can be formed.
(Third Prior Art Method)
As a method for forming a minute gate electrode, a dummy gate method shown in FIG. 3 is known conventionally. For example, Japanese Unexamined Patent Publication No. 62-90979 discloses such a method. In the third prior art method, a dummy gate 12 is formed with a resist on a compound semiconductor substrate 1 with a source electrode 2 and a drain electrode 3 formed thereon (FIG. 3A). Then, by forming an insulating film 13 for reversing the dummy gate 12, on the dummy gate 12 and on the semiconductor substrate 1 (FIG. 3B), and removing the dummy gate 12, a reverse opening pattern 14 is formed in the insulating film 13 (FIG. 3C). Afterwards, an upper resist 6 is applied on the insulating film 13, and an inverted tapered opening 7 is formed in the upper resist 6, facing to the opening 14 of the insulating film 13 (FIG. 3D). Then, by depositing a gate metal on the semiconductor substrate 1 through the opening 7 of the upper resist 6 and the inverted opening pattern 14 of the insulating film 13, and removing the unnecessary gate electrode and the upper resist 6, a T-section gate electrode 8 is formed by the lift-off method (FIG. 3E). Compared with the resolution limit of an ordinary light exposure method of 0.5 .mu.m, the gate length of the gate electrode can further be made minute by processing the dummy gate 12 minutely in the dummy gate method.
Moreover, it is known that a minute pattern of about 0.3 .mu.m can be obtained easily with a light pattern by using a phase shift mask for producing a dummy gate 12 as disclosed for example, in Japanese Unexamined Patent Publication No. 5-136018. The phase shift mask 15 is, as shown in FIG. 4, a transparent photo mask 16 provided with a shifter 17 thereon. When the phase shift mask 15 is irradiated with an ultraviolet ray, the intensity distribution of a light transmitted by the phase shift mask 15 is enlarged locally at the edges of the shifter 17. Therefore, by exposing a positive type resist with the phase shift mask 15, the minute dummy gate 12 can be produced on the semiconductor substrate 1, and finally, the gate electrode 8 with a minute gate length can be obtained.
However, by the method of providing the opening 5 for forming a gate electrode in the lower resist 4 by light exposure as in the above-mentioned first prior art method, a gate length of about 0.5 .mu.m is the limit, and it is very difficult to realize a minute gate length shorter than about 0.5 .mu.m.
Moreover, by the method of using the mixing layer 10 as in the above-mentioned second prior art method, since the mixing layer 10 is formed by the die pattern for forming the mixing layer (the opening 5 of the lower resist 4), a 0.4 .mu.m gate length is the limit with respect to the 0.5 .mu.m limit of the ordinary light exposure method. Furthermore, this method also has a problem in that the phase shift mask method, which is effective in achieving a minute gate pattern, cannot be used. Although a phase shift mask 15 can be used for forming an opening 5 in a lower resist 4, with a negative type resist used for the lower resist 4, the negative type resist has, in general, a poor resolution, and thus a minute pattern cannot be obtained. Besides, a high resolution negative type resist represented by the chemically amplified type has a poor reproductivity, and is difficult in control.
Further, although a minute gate length can be realized by the method of forming the gate electrode 8, using the dummy gate 12 as in the above-mentioned third prior art method, realization of a further minute gate length is desired. Furthermore, since the insulating film 13 exists in the vicinity of the T-section gate electrode in the method using the dummy gate 12, a problem is involved in that the gate parasitic capacity is increased so that the high frequency characteristics of the field effect transistor are deteriorated. Besides, since large size equipment is needed for forming the insulating film 13 to be used for reversing the dummy gate 12, the production cost is increased, and moreover, damage is easily introduced into the semiconductor substrate 1.